1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise strain-inducing semiconductor alloys and gate structures of increased capacitance including a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, complementary transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows subsequent high temperature processes to be carried out, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon and/or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling has to be maintained that is provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage, and thus reduced threshold voltage, may suffer from an exponential increase of the leakage current since the thickness of the silicon dioxide based gate dielectric layer is usually correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. As a consequence, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide based gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits.
Therefore, replacing silicon dioxide based material as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), with a k of about 20, HfSiO, zirconium oxide (ZrO2) and the like.
In addition to incorporating a high-k dielectric, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Furthermore, it is difficult to achieve the required work function and thus threshold voltage values on the basis of doped polysilicon when using high-k dielectric materials. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance and maintains leakage currents at an acceptable level. On the other hand, a non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone and imparting an appropriate work function to the gate electrode.
After forming sophisticated gate structures including a high-k dielectric and a metal-based gate material, however, high temperature treatments may be required, which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, thereby offsetting many of the advantages of the high-k dielectric in combination and the metal material. It is believed that the deterioration of the high-k metal gate is substantially caused by the incorporation of oxygen and respective oxygen diffusion within the high-k dielectric material, wherein the oxygen diffusion may be fed by oxygen contained in the ambient that may come into contact with the high-k dielectric during the processing of the devices.
In addition to a significant modification of the high-k dielectric material, also the work function of the metal in the gate stack may be shifted towards the center of the band gap, thereby modifying the threshold voltage of respective transistors. Due to the high oxygen affinity of the high-k dielectric material and the exposure to wet chemical etch procedures and cleaning processes, usually the gate stack is encapsulated after the patterning process in order to enhance stability of the high-k dielectric material and the respective metals in the gate stack. For this purpose, silicon nitride has proven to be a promising material due to its oxygen blocking characteristics. Hence, in typical conventional process flows, a silicon nitride liner with a thickness in the range of approximately 1-5 nm may be formed on exposed surface areas of the patterned high-k gate stack, wherein appropriate deposition techniques are used so as to not unduly affect device characteristics and/or the subsequent manufacturing steps. For example, well-established low pressure chemical vapor deposition (LPCVD) techniques may be applied for forming the silicon nitride liner.
In addition to providing sophisticated gate electrode structures by using high-k dielectric materials and metal-containing gate electrode materials, other approaches have been developed in order to enhance transistor performance for a given gate length and a thickness of a gate dielectric material. For example, by creating a certain strain in the channel region of the transistor elements, the charge carrier mobility, and thus the overall conductivity of the channel, may be enhanced. For a silicon material having a standard crystallographic configuration, i.e., a (100) surface orientation, with the channel length direction oriented along a <110> equivalent direction, the creation of compressive strain in the current flow direction may increase hole mobility and thus provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past which may per se require a complex manufacturing sequence for implementing the various strain-inducing techniques. For example, one promising approach that is frequently applied is the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors. For this purpose, in an early manufacturing stage, cavities are formed selectively adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer. Additionally, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose the gate electrode material to the etch ambient for forming the cavities and also for providing an efficient growth mask during the selective epitaxial growth process, in which the silicon/germanium alloy may be grown on a crystalline substrate material, while a significant deposition of the alloy on dielectric surface areas may be suppressed by appropriately selecting the corresponding process parameters.
A corresponding strain-inducing mechanism is a very efficient concept for improving transistor performance of P-channel transistors and, therefore, a combination with sophisticated gate electrode structures on the basis of high-k dielectric materials and metal gate electrodes is a very promising approach. Consequently, respective process strategies have been developed in which high-k metal gate electrode structures are formed in an early manufacturing stage, wherein, after the gate patterning process, a strain-inducing silicon/germanium alloy is formed in the drain and source areas of P-channel transistors. It turns out, however, that, although representing a promising process strategy, upon further reducing the gate length of the transistors, significant variations of transistor characteristics and reduced yield may be observed, as will be described in more detail with reference to FIGS. 1a-1j. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing stage in which gate electrode structures 160a, 160b are formed on respective active regions 102a, 102b of the device 100. The active regions 102a, 102b are to be understood as semiconductor regions formed in a semiconductor layer 102, such as a silicon layer and the like, which in turn is formed above an appropriate substrate 101, such as a semiconductor substrate and the like. It should be appreciated that the substrate 101 is typically provided in the form of a wafer comprising a plurality of die regions (not shown), each of which in turn may include a plurality of active regions 102a, 102b, depending on the overall complexity of the circuitry to be formed in a single die region. Furthermore, a buried insulating material (not shown) may be provided below the semiconductor layer 102 if, for instance, an SOI (silicon-on-insulator) architecture is contemplated. The active regions 102a, 102b are typically laterally delineated by appropriate isolation structures (not shown), such as shallow trench isolations and the like. In the example shown, the active region 102a is basically of opposite conductivity type compared to the active region 102b so as to allow the fabrication of transistors of different conductivity type. For example, the active region 102a may correspond to a P-channel transistor. In the manufacturing stage shown, the gate electrode structures 160a, 160b may have a very similar configuration and may comprise a gate dielectric layer 163, which may comprise two or more sub-layers, depending on the overall process and device requirements. For example, a very thin conventional dielectric base layer 161, such as a silicon dioxide material, a nitrogen-enriched silicon dioxide material and the like, may be provided in combination with a high-k dielectric material 162, such as hafnium oxide and the like. It should be appreciated that two or more different high-k dielectric materials may be incorporated in the gate dielectric layer 163, if required. Furthermore, a metal-containing electrode material 164, such as titanium nitride and the like, is typically formed on the gate dielectric layer 163, followed by a further electrode material 165, such as silicon and the like. It should be appreciated that, in principle, these components may be provided in both the gate electrode structure 160a and the gate electrode structure 160b, however, these components may nevertheless differ, for instance, with respect to a work function metal species (not shown), which may be incorporated in the gate dielectric layer 163 and/or in the metal-containing electrode material 164. In this manner, an appropriate work function and thus threshold voltage may be adjusted. Moreover, the gate electrode structures 160a, 160b comprise a dielectric cap layer or layer system 166, for instance comprised of silicon nitride, possibly in combination with a thin silicon dioxide etch stop liner (not shown) and the like. As discussed above, in sophisticated applications, a length of the gate electrode structures 160a, 160b, i.e., the horizontal extension of the electrode material 164, may be 50 nm and significantly less.
Furthermore, frequently, a further band gap offset of transistors of different conductivity type or generally of different characteristics may be required, which is accomplished by incorporating an appropriate semiconductor alloy 102c in the active region 102a of one type of transistor. For example, frequently, a silicon/germanium alloy is provided as the material 102c with a well-defined germanium concentration and a corresponding layer thickness in order to adjust the electronic characteristics of a channel region of a transistor still to be formed in and above the active region 102a. To this end, the layer 102c may be provided with a thickness of 8-20 Å with a germanium concentration of 10-30 atomic percent, thereby efficiently adjusting the finally obtained transistor characteristics, for instance in terms of threshold voltage.
Furthermore, in the manufacturing stage shown, a spacer layer 167, which may be comprised of a liner 167a and a further layer 167b, is typically formed above the active regions 102a, 102b, wherein the thickness and the material characteristics of the spacer layer 167 are selected in view of increasing integrity of sensitive materials, such as the materials 162 and 164, and in view of adjusting an appropriate lateral offset of cavities to be formed in the active region 102a in a later manufacturing stage. To this end, silicon nitride base materials have proven to be viable candidates in order to provide a dense material layer with well-defined thickness.
The semiconductor device 100 as shown in FIG. 1 a is typically formed on the basis of the following processes. The active regions 102a, 102b are typically formed by incorporating an appropriate isolation structure by using sophisticated lithography, patterning, deposition, planarization and anneal techniques, thereby providing the isolation structures with appropriate lateral dimensions, which in turn define the size and shape of the active regions 102a, 102b. Prior to or after forming the isolation structures, the basic transistor characteristics may be adjusted by incorporating appropriate dopant species into the active regions 102a, 102b. Furthermore, prior to or after forming the isolation structures, the semiconductor alloy 102c, for instance in the form of a silicon/germanium alloy, is formed, for instance on the basis of well-established epitaxial growth techniques, wherein material composition and thickness are controlled so as to achieve the desired electronic characteristics. Thereafter, the dielectric materials for the gate dielectric layer 163 are deposited, followed by the deposition of appropriate metal-containing materials, which may then be patterned or otherwise treated in order to adjust a work function for corresponding gate electrode structures in accordance with the overall device requirements. Thereafter, the further materials 164, 165 and 166 may be formed by using well-established deposition techniques. Thereafter, sophisticated lithography and patterning strategies are applied, for instance by patterning the layer or layer system 166 and using the same as a hard mask for actually patterning the lower lying material layers, so as to obtain the gate electrode structures 160a, 160b having the desired dimension in a length direction, i.e., the horizontal direction of FIG. 1a, and in a width direction, i.e., a direction perpendicular to the drawing plane of FIG. 1a. As discussed above, after the above patterning sequence and the corresponding cleaning processes which are typically applied, sidewall surface areas of the sensitive materials 162, 164 have to be reliably covered in order to avoid undue changes of the material characteristics, which in turn would otherwise result in pronounced variations of transistor characteristics, such as threshold voltage and the like. To this end, the layer 167 is deposited, for instance by applying appropriate deposition techniques, for instance for forming a high density nitride material in the form of the layer 167a, followed by a low pressure chemical vapor deposition (CVD) process in order to form the layer 167b, which in combination provide an appropriate thickness as required for defining a lateral offset of cavities still to be formed.
FIG. 1b schematically illustrates the device 100 during an etch process 103 in which cavities 104 are formed in the active region 102a, which are subsequently filled with a strain-inducing semiconductor material, such as a silicon/germanium alloy. To this end, an appropriate etch mask 107, such as a resist mask, is formed above so as to cover respective areas in which the cavities 104 are not required. For example, the mask 107 covers the active region 102b comprising the gate electrode structure 160b, which is still covered by the spacer layer 167. On the basis of the etch mask 107, the etch process 103 is performed by using appropriate plasma assisted etch chemistries in order to etch through the spacer layer 167, thereby forming a sidewall spacer or offset spacer 167s of the gate electrode structure 160a. During the etch process 103, the etch chemistry may then be appropriately adapted so as to continue the etching in order to remove material from the active region 102a, thereby increasingly forming the cavities 104, whose lateral offset from the sensitive gate materials, such as the high-k dielectric material 162 and the metal-containing electrode material 164, is determined by the width of the spacer 167s and thus by the width and density of the spacer layer 167 for otherwise given etch parameters. Typically, the etch process 103 is continued until an etch depth of several tenths nanometers is achieved, depending on the requirement with respect to a corresponding strain to be achieved by the silicon/germanium alloy to be formed in the cavities 104. It should be appreciated that, during the etch process 103, also a sidewall of the semiconductor alloy 102c is exposed.
As discussed above, typically the width of the spacers 167s and thus the characteristics of the spacer layer 167 are selected such that a high degree of integrity of sensitive gate materials may be preserved, while at the same time an appropriate reduced lateral offset is adjusted for the cavities 104, since reducing the lateral offset may increase the efficiency of the strain-inducing effects. Furthermore, with respect to overall process efficiency, the spacers 167s may also be used as an appropriate offset spacer upon incorporating drain and source dopant species in a later manufacturing stage. As a consequence, in particular during the etch process 103, exposure of critical materials or a significant reduction of the thickness of the spacers 167s in critical device areas may result in undue interaction of process atmospheres with the sensitive materials, such as the materials 162, 164, during the further processing. Moreover, the material 102c may also be exposed during the further processing, for instance during respective cleaning processes, as will be described later on in more detail.
FIG. 1c schematically illustrates a top view of the device 100, i.e., of the active region 102a, which is enclosed by an isolation structure 106. The gate electrode structure 160a is formed above the active region 102a and extends into the isolation structure 106. As previously explained, overall performance of transistors significantly depends on the gate length, while the total current drive capability is determined for a given gate length by a width W of the corresponding transistor and thus of the corresponding active region 102a. Typically, transistors of different width have to be implemented in complex circuit designs, thereby requiring active regions of different widths. On the other hand, due to typical design rules, the threshold voltage of a specific type of transistor having a defined gate length should be constant, irrespective of the transistor width of corresponding devices. It turns out, however, that a pronounced variation of threshold voltages for different transistor widths for otherwise identical transistor characteristics may be observed, which is assumed to be caused by undue interaction of sensitive materials with process atmospheres. For example, during the above etch sequence, sensitive materials may be exposed or the thickness of the encapsulating silicon nitride material may be significantly reduced, in particular in an area 105, wherein corresponding “edge effect” may thus affect the total transistor characteristics differently for different transistor widths.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage. After etching the cavities 104, appropriate cleaning processes have to be applied in order to remove contaminants generated during the preceding etch sequence, wherein well-established and efficient wet chemical agents are typically used. For example, in a first cleaning step 108, SPM (sulfuric acid/hydrogen peroxide mixture) and APM (ammonium hydroxide/hydrogen peroxide mixture) are typically applied since, in particular, APM has proven to be a highly efficient cleaning agent providing superior surface states with respect to organic and other contaminants. On the other hand, SPM may be advantageously used with respect to removing metal contaminants and the like. On the other hand, it has been observed that APM may interact with silicon/germanium, which may result in modification of material characteristics and removal of a portion of the layer 102c. As discussed above, however, a corresponding modification of the layer 102c may in turn result in a modification of the resulting transistor characteristics, which in turn may have a different effect on the total transistor characteristics, depending on the width of a corresponding transistor. Similarly, SPM, although highly efficient in cleaning surface areas, is known to interact with sensitive high-k dielectric materials, such as hafnium oxide based materials, which may result in a further oxidation of this material, which in turn may later be removed during the subsequent cleaning processing of the device 100. Furthermore, during the cleaning step 108, any exposed or insufficiently protected areas of the metal-containing electrode material 164 may be attacked, which may also contribute to variations of the overall transistor characteristics. Hence, during the cleaning step 108, a more or less pronounced modification of material characteristics may occur which, however, may also significantly depend on the overall process time, thereby contributing to an even more pronounced variability of threshold voltage characteristics with respect to different transistor widths.
Thereafter, a further cleaning step 109 is typically performed, for instance, immediately prior to performing an epitaxial growth process, thereby further removing contaminants, native oxide and the like, so as to prepare exposed surface areas in the cavities 104 for the deposition of a silicon/germanium alloy. As explained before, the process 109 may also “efficiently” remove previously oxidized portions of the sensitive material 162. On the other hand, replacing the very efficient cleaning agent hydrogen fluoride (HF) with any less aggressive cleaning agents may have a negative effect on the subsequent epitaxial growth process.
FIG. 1e schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, a silicon/germanium alloy 151 is formed in the cavities 104 and thus induces a compressive strain in a channel region 152. As discussed above, the silicon/germanium alloy is typically formed on the basis of well-established epitaxial growth recipes wherein process parameters are adjusted such that significant material deposition on dielectric surface areas, such as the silicon nitride layer 167 (FIG. 1d), the cap layer 166 and the spacer 167s is suppressed. Thereafter, a further etch mask 110 is formed so as to cover the gate electrode structure 160a and the active region 102a, while the active region 102b is exposed. On the basis of a further etch process 119, the exposed spacer layer 167 (FIG. 1d) may be etched in order to obtain the spacer elements 167s on the gate electrode structure 160b. Consequently, after the etch process 119, the gate electrode structures 160a, 160b may have substantially the same configuration and the further processing may be continued on the basis of similar conditions for the gate electrode structures 160a, 160b. 
FIG. 1f schematically illustrates the device 100 after the removal of the etch mask 110 (FIG. 1e). In some approaches, drain and source dopant species may be incorporated into the respective active regions 102a, 102b using the spacers 167s as an implantation mask, while the cap layer 166 is still in place. In other cases, the device 100 is subjected to a process sequence in which the dielectric cap layer 166 is selectively removed substantially without affecting the spacers 167s in order to not unduly jeopardize integrity of sensitive gate materials.
FIG. 1g schematically illustrates the semiconductor device 100 in a manufacturing stage in which sacrificial spacers 111 are formed on the spacers 167s, which is typically accomplished by depositing an appropriate spacer material (not shown), such as silicon dioxide when the cap layers 166 are substantially comprised of silicon nitride. In any case, the material for the spacers 111 is selected so as to efficiently protect the spacers 167s and to allow a subsequent removal of the spacers 111 without contributing to undue material removal of the spacers 167s. Hence, after depositing an appropriate spacer material, a plasma assisted etch process is applied so as to form the spacers 111 which, however, may result in a certain degree of material erosion in the active regions 102a, 102b, as indicated by 102r. 
FIG. 1h schematically illustrates the device 100 during an etch process 112, for instance a plasma based etch process, in which the cap layers 166 (FIG. 1g) are removed while the sacrificial spacers 111 preserve integrity of the spacer structure 167s. During the etch process 112, further material may be removed, thereby possibly increasing the recess 102r, which may thus result in a certain degree of material loss of the strain-inducing semiconductor alloy 151. Thereafter, the sacrificial spacers 111 may be removed, for instance, by well-established wet chemical etch chemistries and the like, wherein selective etch recipes may be applied, for instance, for removing silicon dioxide selectively with respect to silicon, silicon nitride and the like.
FIG. 1i schematically illustrates the device 100 in a manufacturing stage in which drain and source dopant species are incorporated into the active regions 102a, 102b on the basis of respective implantation processes 114a, 114b, possibly in combination with the introduction of further well dopant species by applying tilted implantation processes 113a, 113b. In this manner, halo regions may be incorporated, if required. It should be appreciated that the implantation process 114a, 114b and/or 113a, 113b may be carried out prior to or after removing the cap layers 166 (FIG. 1f), depending on the overall process strategy.
FIG. 1j schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, drain and source regions 153 are formed in the active regions 102a, 102b and have respective concentration profiles as required for the characteristics of transistors 150a, 150b, respectively. Moreover, metal silicide regions 154, for instance comprised of nickel silicide and the like, may be formed in the drain and source regions 153. Furthermore, the gate electrode structures 160a, 160b may comprise an additional spacer structure 169, which may have any appropriate configuration in order to allow appropriate profiling of the drain and source regions 153 and adjust a lateral offset of the metal silicide regions 154 with respect to the channel region 152. Furthermore, a metal silicide 168 may also be provided in the gate electrode structures 160a, 160b. 
The transistors 150a, 150b may be formed on the basis of well-established process strategies, for instance by forming the spacer structure 169 and incorporating additional drain and source implantation species followed by high temperature anneal processes in order to adjust the final lateral and vertical dopant profile of the drain and source regions 153. Thereafter, the metal silicide regions 154 and 168 may be formed on the basis of well-established process strategies.
Consequently, the above-described process sequence is basically a very promising approach for incorporating the strain-inducing semiconductor alloy 151 in the context of sophisticated gate electrode structures, wherein, however, uniformity of transistor characteristics may sensitively depend on the characteristics of the threshold voltage adjusting semiconductor alloy 102c for the transistor 150a and the sensitive gate dielectric material 163 in combination with the metal-containing electrode material 164. That is, as discussed above, in particular the process sequence for incorporating the strain-inducing material 151 for the transistor 150a may result in a pronounced dependency of threshold voltage on the width of a corresponding transistor so that, with the various transistor widths required by a certain circuit design, a variation of 100 mV and even more may be observed in the finally obtained semiconductor device. Since a corresponding spread of the threshold voltages is extremely difficult to be taken into consideration during the design of a semiconductor device, the above-described process sequence, although basically very promising, may result in a pronounced yield loss.
According to the situation described above, the present disclosure relates to manufacturing techniques in which high-k metal gate electrode structures may be combined with strain-inducing semiconductor materials, while avoiding or at least reducing the effects of one or more of the problems identified above.